Recently, as semiconductor integrated circuits have become highly integrated, the sizes of discrete elements therein have been reduced. Thus, the lengths and widths of metal or poly-Si wiring interconnects have also been reduced. As will be understood by those skilled in the art, in order to achieve high integration densities, multi-layer wiring interconnects are typically required and these interconnect structures include interlayer electrical connections to ohmically connect multiple levels of wiring together.
FIGS. 1A-1B are cross-sectional views of intermediate structures illustrating a method of forming electrical interconnections between conductive layers, according to the prior art. Referring now to FIGS. 1A-1B, in order to connect a lower conductive layer 101 with an upper conductive layer 105 which is separated therefrom by an insulating layer 102, a mask 103 having openings therein is typically formed by patterning a layer of photoresist. Then, an anisotropic etching step is performed on the exposed portions of the insulating layer 102 using the mask 103 as an anti-etching film, until the lower conductive layer 101 is exposed. Thereafter, the upper conductive layer 105 is deposited in the contact window 104 formed during the etching step. In the event the contact window 104 is formed in accordance with the above described steps, a misalignment error can be generated where the contact window 104 is not exactly aligned opposite the lower conductive layer 101. Moreover, the insulating layer 102 may also be partially over-etched. To compensate for these potential problems, an overlap margin (region "B" in FIGS. 1B and 2) should be formed on the insulating layer 102. Further, the lower conductive layer 101 pattern corresponding to a portion over which the contact window 104 is formed, should be larger than the width of the contact window 104.
FIG. 2 is a layout schematic view of a plurality of conductive layers having contact holes therein, according to the prior art. In FIG. 2, reference "A" represents the size of the contact window 104, reference "C" represents the space between the wiring, and reference "D" represents the wiring pitch. As illustrated by FIGS. 2-3, even if the width of the wiring is reduced (see reference "E" in FIG. 3), the space between the wiring (see reference "F" in FIG. 3), and the size of the contact window 104 should be maintained so that there exists a degree of overlap margin (see reference "G" in FIG. 3). For that reason, the wiring pitch (see reference "H") is not greatly reduced relative to the wiring pitch "D" illustrated by FIG. 2. Therefore, the width of the entire layout is typically not reduced substantially.
Accordingly, as shown in FIG. 4, in the event a method for reducing the area includes arranging the contact holes 104 in a staggered sequence to reduce the overall area required by the wiring interconnects, the area of the layout can be substantially greatly reduced relative to the layout of FIG. 2. Unfortunately, there is a limitation in that the width of the overlap margin "I" typically cannot be substantially reduced.
Thus, notwithstanding the above described methods, there continues to be a need for improved methods of forming electrical connections between conductive layers.